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eol product document no. e0360e20 (ver. 2.0) date published may 2003 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2003 data sheet 256mb unbuffered ddr sdram dimm ebd25uc8aafa (32m words 64 bits, 1 rank) description the ebd25uc8aafa is 32m words 64 bits, 1 rank double data rate (ddr) sdram unbuffered module, mounting 8 pieces of 256m bits ddr sdram sealed in tsop package. read and write operations are performed at the cross points of the ck and the /ck. this high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. data strobe (dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode register, the on-chip delay locked loop (dll) can be set enable or disable. this module provides high density mounting without utilizing surface mount technology. decoupling capacitors are mounted beside each tsop on the module board. features ? 184-pin socket type dual in line memory module (dimm) ? pcb height: 31.75mm ? lead pitch: 1.27mm ? 2.5v power supply ? data rate: 266mbps (max.) ? 2.5 v (sstl_2 compatible) i/o ? double data rate architecture; two data transfers per clock cycle ? bi-directional, data strobe (dqs) is transmitted /received with data, to be used in capturing data at the receiver ? data inputs and outputs are synchronized with dqs ? 4 internal banks for concurrent operation (component) ? dqs is edge aligned with data for reads; center aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data referenced to both edges of dqs ? auto precharge option for each burst access ? programmable burst length: 2, 4, 8 ? programmable /cas latency (cl): 2, 2.5 ? refresh cycles: (8192 refresh cycles /64ms) ? 7.8 s maximum average periodic refresh interval ? 2 variations of refresh ? auto refresh ? self refresh
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 2 ordering information part number data rate mbps (max.) component jedec speed bin (cl-trcd-trp) package contact pad mounted devices EBD25UC8AAFA-7B 266 ddr266b (2.5-3-3) 184-pin dimm gold m2s56d30atp-75 pin configurations 1 pin front side back side 52 pin 53 pin 92 pin 93 pin 144 pin 145 pin 184 pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 47 nc 93 vss 139 vss 2 dq0 48 a0 94 dq4 140 nc 3 vss 49 nc 95 dq5 141 a10 4 dq1 50 vss 96 vdd 142 nc 5 dqs0 51 nc 97 dm0/dqs9 143 vdd 6 dq2 52 ba1 98 dq6 144 nc 7 vdd 53 dq32 99 dq7 145 vss 8 dq3 54 vdd 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 vdd 11 vss 57 dq34 103 nc 149 dm4/dqs13 12 dq8 58 vss 104 vdd 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vdd 61 dq40 107 dm1/dqs10 153 dq44 16 ck1 62 vdd 108 vdd 154 /ras 17 /ck1 63 /we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vdd 19 dq10 65 /cas 111 nc 157 /cs0 20 dq11 66 vss 112 vdd 158 nc 21 cke0 67 dqs5 113 nc 159 dm5/dqs14 22 vdd 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 vdd 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vdd 27 a9 73 dq49 119 dm2/dqs11 165 dq52 28 dq18 74 vss 120 vdd 166 dq53 29 a7 75 /ck2 121 dq22 167 nc 30 vdd 76 ck2 122 a8 168 vdd
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 31 dq19 77 vdd 123 dq23 169 dm6/dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vdd 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vddid 128 vdd 174 dq60 37 a4 83 dq56 129 dm3/dqs12 175 dq61 38 vdd 84 dq57 130 a3 176 vss 39 dq26 85 vdd 131 dq30 177 dm7/dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 vss 88 dq59 134 nc 180 vdd 43 a1 89 vss 135 nc 181 sa0 44 nc 90 nc 136 vdd 182 sa1 45 nc 91 sda 137 ck0 183 sa2 46 vdd 92 scl 138 /ck0 184 vddspd
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 4 pin description pin name function a0 to a12 address input row address a0 to a12 column address a0 to a9 ba0, ba1 bank select address dq0 to dq63 data input/output /ras row address strobe command /cas column address strobe command /we write enable /cs0 chip select cke0 clock enable ck0 to ck2 clock input /ck0 to /ck2 differential clock input dqs0 to dqs7 input and output data strobe dm0 to dm7/dqs9 to dqs16 input mask scl clock input for serial pd sda data input/output for serial pd sa0 to sa2 serial address input vdd power for internal circuit vddspd power for serial eeprom vref input reference voltage vss ground vddid vdd identification flag nc no connection
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 5 serial pd matrix byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80h 128 bytes 1 total number of bytes in serial pd device 0 0 0 0 1 0 0 0 08h 256 bytes 2 memory type 0 0 0 0 0 1 1 1 07h ddr sdram 3 number of row address 0 0 0 0 1 1 0 1 0dh 13 4 number of column address 0 0 0 0 1 0 1 0 0ah 10 5 number of dimm ranks 0 0 0 0 0 0 0 1 01h 1 6 module data width 0 1 0 0 0 0 0 0 40h 64 7 module data width continuation 0 0 0 0 0 0 0 0 00h 0 8 voltage interface level of this assembly 0 0 0 0 0 1 0 0 04h sstl2 9 ddr sdram cycle time, cl = 2.5 0 1 1 1 0 1 0 1 75h 7.5ns *1 10 sdram access from clock (tac) 0 1 1 1 0 1 0 1 75h 0.75ns *1 11 dimm configuration type 0 0 0 0 0 0 0 0 00h none. 12 refresh rate/type 1 0 0 0 0 0 1 0 82h 7.6 s 13 primary sdram width 0 0 0 0 1 0 0 0 08h 8 14 error checking sdram width 0 0 0 0 0 0 0 0 00h none. 15 sdram device attributes: minimum clock delay back-to-back column access 0 0 0 0 0 0 0 1 01h 1 clk 16 sdram device attributes: burst length supported 0 0 0 0 1 1 1 0 0eh 2,4,8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04h 4 18 sdram device attributes: /cas latency 0 0 0 0 1 1 0 0 0ch 2, 2.5 19 sdram device attributes: /cs latency 0 0 0 0 0 0 0 1 01h 0 20 sdram device attributes: /we latency 0 0 0 0 0 0 1 0 02h 1 21 sdram module attributes 0 0 1 0 0 0 0 0 20h differential clock 22 sdram device attributes: general 1 1 0 0 0 0 0 0 c0h vdd 0.2v 23 minimum clock cycle time at cl = 2 1 0 1 0 0 0 0 0 a0h 10ns *1 24 maximum data access time (tac) from clock at cl = 2 0 1 1 1 0 1 0 1 75h 0.75ns *1 25 to 26 0 0 0 0 0 0 0 0 00h 27 minimum row precharge time (trp) 0 1 0 1 0 0 0 0 50h 20ns 28 minimum row active to row active delay (trrd) 0 0 1 1 1 1 0 0 3ch 15ns 29 minimum /ras to /cas delay (trcd) 0 1 0 1 0 0 0 0 50h 20ns 30 minimum active to precharge time (tras) 0 0 1 0 1 1 0 1 2dh 45ns 31 module rank density 0 1 0 0 0 0 0 0 40h 256m bytes 32 address and command setup time before clock (tis) 1 0 0 1 0 0 0 0 90h 0.9ns *1 33 address and command hold time after clock (tih) 1 0 0 1 0 0 0 0 90h 0.9ns *1
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 34 data input setup time before clock (tds) 0 1 0 1 0 0 0 0 50h 0.5ns *1 35 data input hold time after clock (tdh) 0 1 0 1 0 0 0 0 50h 0.5ns *1 36 to 40 superset information 0 0 0 0 0 0 0 0 00h future use 41 active command period (trc) 0 1 0 0 0 0 0 1 41h 65ns *1 42 auto refresh to active/ auto refresh command cycle (trfc) 0 1 0 0 1 0 1 1 4bh 75ns *1 43 sdram tck cycle max. (tck max.) 0 0 1 1 1 1 0 0 3ch 15ns *1 44 dout to dqs skew 0 0 1 1 0 0 1 0 32h 0.5ns *1 45 data hold skew (tqhs) 0 1 1 1 0 1 0 1 75h 0.75ns *1 46 to 61 superset information 0 0 0 0 0 0 0 0 00h future use 62 spd revision 0 0 0 0 0 0 0 0 00h 63 checksum for bytes 0 to 62 1 1 1 0 1 1 1 0 eeh 64 to 65 manufacturer?s jedec id code 0 1 1 1 1 1 1 1 7fh continuation code 66 manufacturer?s jedec id code 1 1 1 1 1 1 1 0 feh elpida memory 67 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00h 72 manufacturing location (ascii-8bit code) 73 module part number 0 1 0 0 0 1 0 1 45h e 74 module part number 0 1 0 0 0 0 1 0 42h b 75 module part number 0 1 0 0 0 1 0 0 44h d 76 module part number 0 0 1 1 0 0 1 0 32h 2 77 module part number 0 0 1 1 0 1 0 1 35h 5 78 module part number 0 1 0 1 0 1 0 1 55h u 79 module part number 0 1 0 0 0 0 1 1 43h c 80 module part number 0 0 1 1 1 0 0 0 38h 8 81 module part number 0 1 0 0 0 0 0 1 41h a 82 module part number 0 1 0 0 0 0 0 1 41h a 83 module part number 0 1 0 0 0 1 1 0 46h f 84 module part number 0 1 0 0 0 0 0 1 41h a 85 module part number 0 0 1 0 1 1 0 1 2dh ? 86 module part number 0 0 1 1 0 1 1 1 37h 7 87 module part number 0 1 0 0 0 0 1 0 42h b 88 to 90 module part number 0 0 1 0 0 0 0 0 20h (space) 91 revision code 0 0 1 1 0 0 0 0 30h initial 92 revision code 0 0 1 0 0 0 0 0 20h (space) 93 manufacturing date year code (hex) 94 manufacturing date week code (hex) 95 to 98 module serial number 99 to 127 manufacture specific data note: 1. these specifications are defined based on component specification, not module.
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 7 block diagram dq dqs dm dq0 to dq7 * u1, u3, u6, u8, u11, u13, u14, u16 : 256m bits ddr sdram u20: 2k bits eeprom rs: 22 ? notes: 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve "high" state. 8 dqs0 dm0/dqs9 rs rs rs /cs u1 /cs0 dq dq8 to dq15 8 dqs1 dm1/dqs10 rs rs rs u11 dq dq16 to dq23 8 dqs2 dm2/dqs11 rs rs rs u3 dq dq24 to dq31 8 dqs3 dm3/dqs12 rs rs rs u13 dq dq32 to dq39 8 dqs4 dm4/dqs13 rs rs rs u14 dq dq40 to dq47 8 dqs5 dm5/dqs14 rs rs rs u6 dq dq48 to dq55 8 dqs6 dm6/dqs15 rs rs rs u16 dq dq56 to dq63 8 dqs7 dm7/dqs16 rs rs rs u8 a0 to a12 (u1, u3, u6, u8, u11, u13, u14, u16) ba0, ba1 (u1, u3, u6, u8, u11, u13, u14, u16) /ras (u1, u3, u6, u8, u11, u13, u14, u16) /cas (u1, u3, u6, u8, u11, u13, u14, u16) (u1, u3, u6, u8, u11, u13, u14, u16) (u1, u3, u6, u8, u11, u13, u14, u16) cke0 u1, u3, u6, u8, u11, u13, u14, u16 u1, u3, u6, u8, u11, u13, u14, u16 vdd vss vref vddid open clock wiring note: wire per clock loading table/wiring diagrams. dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs clock input ck0, /ck0 ck1, /ck1 ck2, /ck2 ddr sdrams 2dram loads 3dram loads 3dram loads serial pd sda a0 a1 a2 sa0 sa1 sa2 scl scl u20 sda a0 to a12 ba0, ba1 /ras /cas /we u1, u3, u6, u8, u11, u13, u14, u16
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 8 logical clock net structure r = 120 ? ? ? ? ? ?
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 9 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?0.5 to +3.6 v supply voltage relative to vss vdd ?0.5 to +3.6 v short circuit output current ios 50 ma power dissipation pd 8 w operating ambient temperature ta 0 to +70 c 1 storage temperature tstg ?40 to +100 c notes: 1. ddr sdram component specification. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating conditions (ta = 0 to +70c) (ddr sdram component specification) parameter symbol min typ max unit notes supply voltage vdd,vddq 2.3 2.5 2.7 v 1 vss 0 0 0 v input reference voltage vref 0.49 vddq 0.50 vddq 0.51 vddq v termination voltage vtt vref ? 0.04 vref vref + 0.04 v input high voltage vih (dc) vref + 0.15 ? vddq + 0.3 v 2 input low voltage vil (dc) ?0.3 ? vref ? 0.15 v 3 input voltage level, ck and /ck inputs vin (dc) ?0.3 ? vddq + 0.3 v 4 input differential cross point voltage, ck and /ck inputs vix (dc) 0.5 vddq ? 0.2v 0.5 vddq 0.5 vddq + 0.2v v input differential voltage, ck and /ck inputs vid (dc) 0.36 ? vddq + 0.6 v 5, 6 notes: 1. vddq must be lower than or equal to vdd. 2. vih is allowed to exceed vdd up to 3.6v for the period shorter than or equal to 5ns. 3. vil is allowed to outreach below vss down to ?1.0v for the period shorter than or equal to 5ns. 4. vin (dc) specifies the allowable dc execution of each differential input. 5. vid (dc) specifies the input differential voltage required for switching. 6. vih (ck) min assumed over vref + 0.18v, vil (ck) max assumed under vref ? 0.18v if measurement.
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 10 dc characteristics 1 (ta = 0 to +70c, vdd = 2.5v 0.2v, vss = 0v) parameter symbol grade max. unit test condition notes operating current (actv-pre) idd0 680 ma cke vih, trc = trc (min.) 1, 2, 9 operating current (actv-read-pre) idd1 800 ma cke vih, bl = 4, cl = 2.5, trc = trc (min.) 1, 2, 5 idle power down standby current idd2p 48 ma cke vil 4 floating idle standby current idd2f 240 ma cke vih, /cs vih dq, dqs, dm = vref 4, 5 active power down standby current idd3p 120 ma cke vil 3 active standby current idd3n 360 ma cke vih, /cs vih tras = tras (max.) 3, 5, 6 operating current (burst read operation) idd4r 1200 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 operating current (burst write operation) idd4w 1120 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 auto refresh current idd5 1120 ma trfc = trfc (min.), input vil or vih self refresh current idd6 24 ma input vdd ? 0.2 v input 0.2 v operating current (4 banks interleaving) idd7a 1880 ma bl = 4 5, 6, 7 notes: 1. these idd data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one cycle. 6. data/data mask transition twice per one cycle. 7. 4 banks active. only one bank is running at trc = trc (min.) 8. the idd data on this table are measured with regard to tck = tck (min.) in general. 9. command/address transition once per one every two clock cycles. dc characteristics 2 (ta = 0 to +70c, vdd, vddq = 2.5v 0.2v, vss = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ?16 16 a vdd vin vss output leakage current ilo ?5 5 a vdd vout vss output high current ioh ?16.8 ? ma vout = vtt + 0.84v 1 output low current iol 16.8 ? ma vout = vtt ? 0.84v 1 note: 1. ddr sdram component specification.
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 11 pin capacitance (ta = 25c, vdd = 2.5v 0.2v) parameter symbol pins max. unit notes input capacitance ci1 address, /ras, /cas, /we, /cs, cke 75 pf input capacitance ci2 ck, /ck 60 pf data and dqs input/output capacitance co dq, dqs 10 pf ac characteristics (ta = 0 to +70 c, vdd, vddq = 2.5v 0.2v, vss = 0v) (ddr sdram componen specification) parameter symbol min. max unit notes clock cycle time (cl = 2) tck 10 15 ns (cl = 2.5) tck 7.5 15 ns ck high-level width tch 0.45 0.55 tck ck low-level width tcl 0.45 0.55 tck ck half period thp min (tch, tcl) ? tck dq output access time from ck, /ck tac ?0.75 0.75 ns dqs output access time from ck, /ck tdqsck ?0.75 0.75 ns dqs to dq skew tdqsq ? 0.5 ns dq/dqs output hold time from dqs tqh thp ? 0.75 ? ns data-out high-impedance time from ck, /ck thz ?0.75 0.75 ns 1 data-out low-impedance time from ck, /ck tlz ?0.75 0.75 ns 1 read preamble trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck dq and dm input setup time tds 0.5 ? ns dq and dm input hold time tdh 0.5 ? ns dq and dm input pulse width tdipw 1.75 ? ns write preamble setup time twpres 0 ? ns 3 write preamble twpre 0.25 ? tck write postamble twpst 0.4 0.6 tck 2 write command to first dqs latching transition tdqss 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? tck dqs input high pulse width tdqsh 0.35 ? tck dqs input low pulse width tdqsl 0.35 ? tck address and control input setup time tis 0.9 ? ns 6 address and control input hold time tih 0.9 ? ns 6 mode register set command cycle time tmrd 15 ? ns active to precharge command period tras 45 120000 ns active to active/auto refresh command period trc 65 ? ns auto refresh to active/auto refresh command period trfc 75 ? ns active to read/write delay trcd 20 ? ns precharge to active command period trp 20 ? ns
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 12 parameter symbol min. max unit notes active to active command period trrd 15 ? ns write recovery time twr 15 ? ns auto precharge write recovery and precharge time tdal 35 ? ns internal write to read command delay twtr 1 ? tck exit self refresh to non-read command txsnr 75 ? ns exit self refresh to read command txsrd 200 ? tck exit power down to any non-read command txpnr 1 ? tck exit precharge power down to read command txprd 1 ? tck 5 average periodic refresh interval tref ? 7.8 s 4 notes: 1 thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 2. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 4. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 5. txprd should be 200 tck in the condition of the unstable ck operation during the power down mode. 6. for command/address and ck and /ck slew rate 1.0v/ns.
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 13 timing parameter measured in clock cycle for unbuffered dimm number of clock cycle parameter symbol min. max. unit write to pre-charge command delay (same bank) twpd 3 + bl/2 tck read to pre-charge command delay (same bank) trpd bl/2 tck write to read command delay (to input all data) twrd 2 + bl/2 tck burst stop command to write command delay (cl = 2) tbstw 2 tck (cl = 2.5) tbstw 3 tck burst stop command to dq high-z (cl = 2) tbstz 2 2 tck (cl = 2.5) tbstz 2.5 2.5 tck read command to write command delay (to output all data) (cl = 2) trwd 2 + bl/2 tck (cl = 2.5) trwd 3 + bl/2 tck pre-charge command to high-z (cl = 2) thzp 2 2 tck (cl = 2.5) thzp 2.5 2.5 tck write command to data in latency twcd 1 1 tck write recovery twr 2 tck dm to data in latency tdmd 0 0 tck mode register set command cycle time tmrd 2 tck self refresh exit to non-read command tsnr 75 tck self refresh exit to read command tsrd 200 tck power down exit to command input tpdex 1 tck
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 14 pin functions ck, /ck (input pin) the ck and the /ck are the master clock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the ck rising edge and the vref level. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are referred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. /cs (input pin) when /cs is low, commands and data can be input. w hen /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 to a12 (input pins) row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the vref level in a bank active command cycle. column address (ay0 to ay9) is loaded via the a0 to the a9 at the cross point of the ck rising edge and the vref level in a read or a write command cycle. this column address becomes the starting address of a burst operation. a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1, ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0, ba1 (input pin) ba0, ba1 are bank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. cke (input pin) cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 ck cycle at least, that is, if cke changes at the cross point of the ck rising edge and the vref level with proper setup time tis, at the next ck rising edge cke level must be kept with proper hold time tih. dq (input and output pins) data are input to and output from these pins. dqs (input and output pin) dqs provide the read data strobes (as output) and the write data strobes (as input).
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 15 dm (input pins): dm is the reference signal of the data input mask function. dms are sampled at the cross point of dqs and vref vdd (power supply pins) 2.5v is applied. (vdd is for the internal circuit.) vddspd (power supply pin) 2.5v is applied (for serial eeprom). vss (power supply pin) ground is connected. detailed operation part and timing waveforms refer to m2s56d20/30/40atp datasheet.
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 16 physical outline detail a 0.20 0.15 2.50 0.20 1.27 (datum -a-) 2.30 64.77 49.53 (64.48) a b 1 92 93 r 2.00 184 1.00 0.05 unit: mm 1.27 0.10 3.00 4.00 min 10.00 4.00 17.80 31.75 3.18max component area (front) (back) 6.35 detail b 3.80 1.80 0.10 2.175 6.62 r 0.90 (datum -a-) eca-ts2-0094-01 128.95 133.35 2 ?
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 17 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
eol product ebd25uc8aafa data sheet e0360e20 (ver. 2.0) 18 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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